Gerhard P. Fettweis, earned a Ph.D. under H. Meyr at RWTH Aachen (Germany) in 1990. After a postdoc at IBM Research, San Jose, he joined TCSI, Berkeley, USA. Since 1994 he is Vodafone Chair Professor at TU Dresden, Germany. Since 2018 he is also founding Scientific Director & CEO of the Barkhausen Institute. He researches wireless communications and chip design, coordinates 5G++Lab Germany and the German Cluster-for-Future SEMECO. His team spun-out 32 tech startups, and he initiated 6 platform entities. Gerhard is member of the US National Academy of Engineering, the German Academy of Sciences (Leopoldina), the German Academy of Engineering (Acatech), the Bavarian Academy of Sciences, and Fellow of IEEE, VDE/ITG, National Academy of Inventors, EURASIP, WWRF, and DATE. He is active in organizing IEEE conferences.

The Masur SoC Platform: From Educational Framework to Product-Grade Integration

System-on-chip (SoC) design is increasingly complex, requiring the integration of heterogeneous compute cores, accelerators, and scalable on-chip interconnects, together with peripheral interfaces and memory subsystems at board or chiplet level. In addition, the software stack—including boot mechanisms, operating system integration, bring-up, debugging, and maintenance—must be tightly coupled to the hardware platform. Robust security architectures are also required to isolate untrusted IP and ensure resilience against attacks. We address these challenges through the M3-based Masur SoC Platform, a modular integration environment for research, education, and product design. The platform enables rapid incorporation and validation of external IP blocks within a complete SoC framework. Experience from multiple chip runs (Masur 23–26) demonstrates the effectiveness of this approach for testing, debugging, and corner-case evaluation of new designs. Through configurable system composition, the Masur SoC Platform supports both educational exploration and the transition toward application-specific, product-grade SoC implementations.

Prof. Ecker is a Distinguished Engineer at Infineon Technologies and Professor at the Technical University of Munich, Prof. Ecker is a leading expert in digital system modelling, design automation, SoC architectures, embedded AI, and AI for EDA. He has authored 200+ publications, received seven publication awards, and the German EDA Achievement Award, he is recognized as one of the leading experts shaping the future of electronic design automation and intelligent system design. As a member of Acatech – the German Academy of Science and Engineering and a former member of the German Government's AI Commission of Inquiry, Prof. Ecker continues to bridge cutting-edge research with industrial innovation and opportunities for society.

Building One's Own EDA Tools: Ambition, Approach, Achievements

Gain valuable insights into the demand, vision, strategies, and practical experiences behind developing in-house EDA tools, and their role in driving innovation in semiconductor design.

Ulf Schlichtmann holds a doctorate in electrical engineering from Technical University of Munich (TUM), as well as a technology business degree. He spent about 10 years in the semiconductor industry (Siemens, Infineon) in various engineering, management and executive positions, working on design automation, design libraries, IP reuse, and product development. In 2003, he joined TUM as professor and head of the Chair of Electronic Design Automation. Ulf’s current research interests include computer-aided design of electronic circuits and systems, with an emphasis on designing reliable and robust systems. His research especially addresses emerging technologies, such as microfluidic biochips, photonic interconnects, optical computing, and memristor-based neural network accelerators. His research also increasingly considers the opportunities offered by generative AI. Since 2016, Ulf is an elected member of TUM’s Academic Senate, serving as vice chair since 2022, as well as the TUM Board of Trustees. He is a member of the German National Academy of Science and Engineering, and a board member of Germany’s edacentrum. Since 2021, he also serves as CEO of TUM’s Singapore research center, TUMCREATE.

Large Language Models for Front-End Design: First Achievements – and Future Challenges and Opportunities

The growing complexity of modern integrated circuits has significantly increased the demands placed on hardware engineers, particularly within design, simulation, and verification workflows. These processes are inherently iterative and often rely on extensive manual effort, making them time-consuming and prone to errors. Consequently, there is an increasing need for more efficient and scalable Electronic Design Automation (EDA) solutions. Large Language Models (LLMs), which are trained on extensive human knowledge and interact naturally through text, present a promising opportunity to support front-end EDA tasks. By assisting with design generation and verification, LLMs have the potential to substantially improve circuit design productivity. This presentation will demonstrate how LLMs can automate critical stages of the hardware development lifecycle. I will introduce methods for automatically generating circuit designs and their corresponding testbenches from a shared specification, and will illustrate how LLMs can enhance design quality in established workflows such as high-level synthesis. Also, I will discuss the current challenges and limitations of LLM integration in EDA and outline future research opportunities for advancing LLM-enabled front-end design.