September 3-6, 2019
Marina Bay Sands Hotel
Singapore

Wednesday Keynote Speaker


Norbert Wehn
Professor and Chair for Microelectronic System Design

University of Kaiserslautern, Germany

The Memory Wall: Challenges and Solutions”

Wehn

Norbert Wehn holds the chair for Microelectronic System Design in the department of Electrical Engineering and Information Technology at the University of Kaiserslautern. He has more than 300 publications in various fields of microelectronic system design and holds 20 patents. Two start-ups spinout of his research group. His special research interests are VLSI-architectures for mobile communication, forward error correction techniques, low-power techniques, advanced SoC and memory architectures, 3D integration, reliability issues in SoC, IoT and hardware accelerators for big data applications.

Abstract: Current and emerging embedded applications require ever larger amount of data that have to be processed. Due to their large size, this data has to be stored off-chip in Dynamic Random Access Memories (DRAM). The challenges introduced by DRAMs in those systems are manifold. These include limited bandwidth and latency, as well as power consumption and reliability issues. In this talk, we will give an overview on various optimization techniques to optimize bandwidth, power and reliability in DRAM based and emerging memory systems.


Wednesday Plenary Speaker


To be announced


Thursday Keynote Speaker


Massimo Alioto
Professor, head of Green IC group, and Director of Integrated Circuits and Embedded Systems
National University of Singapore, Singapore

Survival of The Fittest: Circuits and Architectures for Computation with Wide Power-Performance Adaptation Beyond Voltage Scaling

massimo1

Massimo Alioto is an Associate Professor at the Department of Electrical and Computer Engineering, National University of Singapore where he leads the Green IC group and is the Director of the Integrated Circuits and Embedded Systems area. Previously, he was Associate Professor at the Department of Information Engineering of the University of Siena. In 2013 he was also Visiting Scientist at Intel Labs – CRL (Oregon) to work on ultra-scalable microarchitectures. In 2011-2012, he was Visiting Professor at University of Michigan, Ann Arbor, investigating on active techniques for resiliency in near-threshold processors, error-aware VLSI design for wide energy scalability, self-powered circuits. In 2009-2011, he was Visiting Professor at BWRC – University of California, Berkeley, investigating on next-generation ultra-low power circuits and wireless nodes. In the summer of 2007, he was a Visiting Professor at EPFL – Lausanne (Switzerland).

A/Prof Alioto received the Laurea (MSc) degree in Electronics Engineering and the Ph.D. degree in Electrical Engineering from the University of Catania (Italy) in 1997 and 2001, respectively.

He has authored or co-authored more than 230 publications on journals (80, mostly IEEE Transactions) and conference proceedings. One of them is the second most downloaded TCAS-I paper in 2013. He is co-author of three books, Enabling the Internet of Things – from Circuits to Networks (Springer, 2017), Flip-Flop Design in Nanometer CMOS – from High Speed to Low Energy (Springer, 2015) and Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits (Springer, 2005). His primary research interests include ultra-low power VLSI circuits, self-powered and wireless nodes, near-threshold circuits for green computing, error-aware and widely energy-scalable VLSI circuits, circuit techniques for emerging technologies.

Abstract:


Thursday Plenary Speaker


to be announced


 

Banquet Speaker


to be announced


 

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