Conference Highlights
For more than 22 years, IEEE SOC Conference has been providing a premier forum for the ASIC and SoC community for sharing the latest advances in technologies and applications in that area. Founded in 1987 by the IEEE chapter of Rochester, NY, USA as a local ASIC Seminar, the conference rapidly grew into a well respected international ASIC conference. As ASICs grew in complexity over the years, the IEEE ASIC Conference was one of the first conferences to pick up the trend towards System-on-Chip integration - back in 1999. Since then, the conference - first renamed IEEE ASIC/SOC and later IEEE SOCC - has emerged as the premier technical conference focusing specifically on the field of SoC development and related areas.
Venue
SOCC 2010 will be held at Bally’s in Las Vegas. Nevada, USA, on Sept. 27-29, 2010
The Conference
In its tradition of continuing quality, SOCC 2010 will offer three days of technical papers and embedded tutorials. Please watch this site for updates on distinguished speakers and the technical program. While we are finalizing the program for 2010, you may as well want to take a look at our previous conferences.
Distinguished Speakers
SOCC has a long tradition of inviting high-ranking invited speakers from industry and academia to give Keynote, Plenary, and Luncheon talks.
A list of our speakers from 1990-2009 can be found here.
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Panel Discussion
Like every year, SOCC 2010 will feature a panel discussion on a hot controversial topic in the SoC area.
Best Paper Award
The authors of the best technical paper will receive a Best Paper Award
Corporate Sponsors and Exhibitors:
Corporate sponsors of our conference may be present with tabletop displays. For more information on corporate sponsorship, please see our sponsorship page
Tutorial Workshops:
Like at our previous conferences, there will be several embedded tutorials during the technical program. For tutorial proposals, please contact the Program Chair.
Keynote Speaker
Alberto Sangiovanni-Vincentelli
Professor, University of California at Berkeley, and
Chief Technology Advisor, Cadence Design Systems
“SoC Design as an Example of Component-Based Design of Distributed
Systems”
Alberto Sangiovanni Vincentelli holds the Edgar L. and Harold H. Buttner Chair of Electrical Engineering and Computer Sciences at the University of California at Berkeley. He has been on the Faculty since
1976. He obtained an electrical engineering and computer science degree ("Dottore in Ingegneria") summa cum laude from the Politecnico di Milano, Milano, Italy in 1971. In 1980-1981, he spent a year as a
Visiting Scientist at the Mathematical Sciences Department of the IBM T.J. Watson Research Center. In 1987, he was Visiting Professor at MIT. He has held a number of visiting professor positions at Italian Universities,
including Politecnico di Torino, Università di Roma, La Sapienza, Università di Roma, Tor Vergata, Università di Pavia, Università di Pisa, Scuola di Sant’ Anna.
He was a co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. He is the Chief Technology Adviser of Cadence. He is a member of the Board of Directors of Cadence and the Chair of its Technology Committee, UPEK, a company he helped spinning off from ST Microelectronics, Sonics, and Accent, an ST Microelectronics-Cadence joint venture he helped founding. He was a member of the HP Strategic Technology Advisory Board, and is a member of the Science and Technology Advisory Board of General Motors and of the Scientific Council of the Tronchetti Provera foundation and of the Snaidero Foundation. He consulted for many companies including Bell Labs, IBM, Intel, United Technologies Corporation, COMAU, Magneti Marelli, Pirelli, BMW, Daimler-Chrysler, Fujitsu, Kawasaki Steel, Sony, ST, United Technologies Corporation and Hitachi. He was an advisor to the Singapore Government for microelectronics and new ventures. He consulted for Greylock Ventures and for Vertex Investment Venture Capital funds. He is a member of the Advisory Board of Walden International, Sofinnova and Innogest Venture Capital funds and a member of the Investment Committee of a novel VC fund, Atlante Ventures, by Banca Intesa/San Paolo. He is the founder and Scientific Director of the Project on Advanced Research on Architectures and Design of Electronic Systems (PARADES), a European Group of Economic Interest supported by Cadence, Magneti-Marelli and ST Microelectronics. He is a member of the Advisory Board of the Lester Center for Innovation of the Haas School of Business and of the Center for Western European Studies and is a member of the Berkeley Roundtable of the International Economy (BRIE). He is a member of the High-Level Group, of the Steering Committee, of the Governing Board and of the Public Authorities Board of the EU Artemis Joint Technology Initiative. He is member of the Scientific Council of the Italian National Science Foundation (CNR).
In 1981, he received the Distinguished Teaching Award of the University of California. He received the worldwide 1995 Graduate Teaching Award of the IEEE (a Technical Field award for “inspirational teaching of graduate students”). In 2002, he was the recipient of the Aristotle Award of the Semiconductor Research Corporation. He has received numerous research awards including the Guillemin-Cauer Award (1982-1983), the Darlington Award (1987-1988) of the IEEE for the best paper bridging theory and applications, and two awards for the best paper published in the IEEE Transactions on CAS and CAD, five best paper awards and one best presentation awards at the Design Automation Conference, other best paper awards at the Real-Time Systems Symposium and the VLSI Conference. In 2001, he was given the Kaufman Award of the Electronic Design Automation Council for “pioneering contributions to EDA”. In 2008, he was awarded the IEEE/RSE Wolfson James Clerk Maxwell Medal ”for groundbreaking contributions that have had an exceptional impact on the development of electronics and electrical engineering or related fields” with the following citation: ”For pioneering innovation and leadership in electronic design automation that have enabled the design of modern electronics systems and their industrial implementation.” In 2009, he received the first ACM/IEEE A. Richard Newton Technical Impact Award in Electronic Design Automation to honor persons for an outstanding technical contribution within the scope of electronic design automation. In 2009, he was awarded an honorary Doctorate by the University of Aalborg in Denmark.
He is an author of over 850 papers, 15 books and 3 patents in the area of design tools and methodologies, large-scale systems, embedded systems, hybrid systems and innovation.
Dr. Sangiovanni-Vincentelli has been a Fellow of the IEEE since 1982 and a Member of the National Academy of Engineering, the highest honor bestowed upon a US engineer, since 1998.
Abstract:
As the complexity of IC design grows, component-based design and correct-by-construction techniques become indispensible to make it possible to develop new application specific designs or even new high volume devices such as microprocessors. While many design methods have been proposed over the years to solve the cost and time-to-market issues, industry is still not able to deploy widely new methods. However, research in recent years has made important inroads, semiconductor companies have implemented more structured design methodologies and EDA/IP enterprises have made significant investment in new tools and design environments. In this talk we will review some of the most interesting approaches that are based on interconnect and communication design as well as heterogeneous composition of components with the goal of pointing out some promising avenues to make SoC design economically attractive for a wide variety of applications
Plenary Speaker
Michael Keating
Fellow,
Synopsys, Inc.
”Third Revolution: The Search for Scalable Code-Based Design”
Mike Keating is a Synopsys Fellow. He has been with Synopsys for
13 years, focusing on IP development methodology, hardware and software design quality and low power design. His current research focuses on high level design and the challenges of designing extremely
complex systems. Mike received his BSEE and MSEE from Stanford University, and has over 25 years experience in ASIC and system design. He is co-author of the Reuse Methodology Manual and the Low Power Methodology Manual. In 2007, ISQED gave Mike the Quality
Award for contributions to quality in electronic design.
Abstract:
Over the last 25 years, there have been two major revolutions in how we do digital design: the move to language/synthesis based design (starting in 1986) and design reuse (starting around 1996). We are well overdue for a third revolution. Current design methods are not meeting the needs dictated by the complexity and size of today’s SoC designs, much less the designs of the future.
This talk will describe the current candidates for the next revolution in digital design: high level synthesis, chip generators, and radical extensions to the synthesizable subset of current RTL languages. It will also describe how the economics of SoC design and manufacturing, as well as the economics of EDA, will affect and possibly de-rail the third revolution.
Plenary Speaker
Sandra Woodward
Senior Technical Staff Member, PowerEN Processor Chip Technical Lead
IBM Corp.
”The IBM Power Edge of Network™ Processor:
A wire-speed System-on-a-Chip (SOC): Technical Overview and Challenges for a Large Complex SOC used in Next-Generation Systems”
Sandra Woodward
is a Senior Technical Staff Member at IBM and is currently the Chip Technical Lead for the “Power Edge of Network” or
“PowerEN” Processor Chip. She is a expert in the area of Microprocessor and Memory Hierarchy Architecture, Design and Methodology. She has experience in System-on-a-Chip (SOC) design,
ASIC design, Power(TM) architecture, and Cache and Coherency function design. Mrs. Woodward holds a B.S. degree in Electrical Engineering (EE) from the University of Nebraska and an M.S. degree in EE from Syracuse University.
Abstract:
This presentation will give a technical overview on one of the most complex chips IBM has ever built: the IBM Power Edge of Network™ Processor System-on-a-Chip (SOC). This includes the general purpose processing subsystem, the special purpose accelerator subsystem, the network I/O subsystem, and the interconnect for on-chip and off-chip coherency. It will explore the challenges and trade-offs made on the PowerEN SOC which is integrated into a Next-Generation System. This includes items such as lower power, increased computational performance, and heterogeneous compute elements. It will also discuss the implications of technology advancement on architectural and functional design decisions and point out problems requiring solutions for the large, complex System-on-a-Chip designs in the future.
Plenary Speaker
Jo Dale Carothers
Partner, Covington & Burling LLP
”What You Need to Know About Patent Litigation”
Jo Dale Carothers is a partner in the San Diego office of the law firm of
Covington & Burling LLP. Her practice emphasizes intellectual property litigation in the field of electrical and computer engineering, including computer-aided design, design automation, semiconductors,
microprocessors, and other areas relating to computer hardware and software.
Dr. Carothers has been active on numerous technical organizing committees and technical program committees for IEEE conferences, such as the program committee for the Design Automation Conference, and she served on the editorial board for the Integrated Computer-Aided Engineering Journal. She served as the vice co-chair of the IEEE 2007 International Conference on Image Processing (ICIP) Conference and serves on the steering committee for the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). Dr. Carothers has published more than 60 journal and conference papers in the field.
Representative Matters
- Silicon Storage Technology, Inc. v. Intersil Corporation, et al. (N.D. Cal.): Representation of Silicon Storage Technology in a declaratory judgment action involving EEPROM devices.
- Advanced Micro Devices v. Samsung, Case No. 3:08-CV-0986-SI. Represents defendant in patent litigation involving circuit, microprocessor, and process patents.
- Fortinet, Inc. v. Trend Micro Incorporated (N.D. Cal.). Represents Trend Micro in patent litigation concerning anti-virus technology.
- UMC, ProMOS, Microchip, and Microna, USITC Inv. No. 337-TA-648. Represented the respondents in this multiparty representation concerning semiconductor integrated circuits.
- Flash Memory Devices, USITC Inv. No. 337-TA-619. Represented multiple respondents in this ITC investigation brought by Sandisk concerning flash memory devices.
- Microchip v. ZiLOG, District of Arizona, Case No. 2:05-cv-2406-MHM. Represents Microchip in a lawsuit alleging infringement of three Microchip microcontroller patents by ZiLOG’s products. These patents relate to reducing the pin count for microcontrollers.
- Microchip v. Luminary Micro, District of Arizona, Case No. 2:06-cv-0986-ROS. Represents Microchip in a lawsuit alleging infringement of three Microchip microcontroller patents by Luminary Micro’s products. These patents relate to reducing the pin count for microcontrollers.
- Disc Link v. Oracle et al., Eastern District of Texas, Case No. 5:06-CV-00295-DF. Represented a group of defendants, including SAP, CA, Kodak, Altera, Novell and Sonic Solutions, in patent litigation regarding hyperlink technology.
Abstract:
This presentation will cover a wide variety of topics that impact an engineer's life before, during and after
patent litigation begins. Topics will include the impact of participation in standards setting committees, the role of a patent inventor during subsequent litigation, engineer's roles as an expert witness, potential
patent reform issues and recent Supreme Court decisions that impact the landscape of patent litigation.
Luncheon Speaker
P.R. Mukund
President and Chief Executive Officer
NanoArk Corp.
“From Film to Silicon: The Migration of Document Archiving Technology”
Dr. P.R. Mukund is the founding President & CEO of NanoArk Corporation, that pioneered the new
WaferficheTM technology. He is also Professor in the Electrical Engineering Department at the Rochester Institute of Technology where he has been the principal
investigator of research projects for over $2 million in the last decade. He has published extensively and was a distinguished lecturer of IEEE Circuits and Systems Society. He also chaired many international conferences
including the IEEE SoC conference.
Dr. Mukund has a BSEE. MS and Ph.D. from the University of Tennessee, Knoxville.
Abstract:
During the last six to seven decades, hundreds of millions of vital records have been archived using
micro-film and micro-fiche technologies. Recently, a sizable number of these have gone bad since they were not stored in strict environmental conditions, such as controlled humidity and temperature.
This talk looks at the migration that has recently taken place in replacing film with Silicon wafers that can withstand both high levels of humidity and extreme temperatures. Examples of manuscripts that are
many centuries old will be presented.