Welcome to our conference program overview !
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CONFERENCE-AT-A-GLANCE

Tuesday, September 16 11:30 a.m. - 5:00 p.m. Tour to NASA Jet Propulsion Lab (JPL)

Wednesday, September 17 Registration 7:00 a.m. - 5:00 p.m.   Plenary Session 8:30 a.m. - 11:55a.m. Opening Remarks:    Thanh Tran, General Conference Chair Technical Program Overview:    Thomas Büchner, Technical Program Chair Keynote Presentation:   Nick Ilyadis, VP and CTO of Enterprise Networking Group, Broadcom Plenary Presentations: Alexander D. Peleg, Vice President, Mobility Group Director, Intel Architecture Strategic and Platform Planning Intel Corporation    Kamran Eshraghian, President, Eshraghian Laboratories Pty Ltd., and Ferrero Family Chair in Electrical Engineering, University of California, Merced. 11:55 a.m. - 1:30 p.m. Lunch (on your own) Technical Sessions 1:30 p.m. - 3:10 p.m. Track A WA2: Embedded Systems and Multicore Architectures Track B WB2: System Level Design 3:30 p.m. - 5:10 p.m. WA3: Signal Integrity WB3: Network on Chip 5:10 p.m. - 6:40 p.m. Poster Session with Reception

Thursday, September 18 Registration 7:30 a.m. - 5:00 p.m.   Technical Sessions 8:30 a.m. - 10:10 a.m. Track A TA1: Low Power Circuit Design Track B TB1: Solutions for H.264 10:30 a.m. - 11:45 a.m. TA2: Low Power Design Methodologies TB2: Video Processing Luncheon 11:45 a.m. - 1:30 p.m. Guest speaker: David F. Doody, Flight Operations Lead, Cassini Mission Support & Services, NASA Jet Propulsion Lab Technical Sessions 1:30 p.m. - 3:10 p.m Track A TA3: SRAM Memory Technologies Track B TB3: Analog and Mixed Signal 1 3:30 p.m. - 4:25 p.m. “Hot Topic” Plenary Presentation: Dynamic Configuration: Beyond Video Coding Standards Iain Richardson, Centre for Video Communications, The Robert Gordon University, UK 4:30 p.m. - 6:00 p.m. Panel Discussion

Friday, September 19 Registration 8:00 a.m. - 3:30 p.m.   Technical Sessions 8:30 a.m. - 10:10 a.m. Track A FA1: Reconfigurable Computing 1 Track B FB1: Analog and Mixed Signal 2 10:30 a.m. - 12:10 p.m. FA2: Reconfigurable Computing 2 FB2: Analog and Mixed Signal 3 12:10 p.m. - 1:30 p.m. Lunch (on your own) 1:30 p.m. - 3:10 p.m. FA3: CAD FB3: Communication and Processing 3:30 p.m. - 5:30 p.m. TFA1: Design and Verification of Complex SoC with Configurable, Extensible Processors TFB1 A New Generation of C-Base Synthesis Tool and Domain-Specific Computing

Saturday, September 20 Morning Workshops Tutorial Track A Tutorial Track B Tutorial Track C 9:00 a.m. - 12:00 noon SA1 Flying-Adder On-Chip Frequency Synthesis Architecture SB1 Low Power Design under Parameter Variations SC1 Real-time implementation of H.264 video coding Afternoon Workshops       13:00 p.m. - 16:00 p.m. SA2 Understanding and Effectively Suppressing the Noise Coupling in Mixed-Signal SOC Applications SB2 Asynchronous Circuit Design using Handshake Solutions