Wednesday, September 17 - Morning

PLENARY SESSION
8:30 a.m. - 11:55 a.m.

Opening Remarks: Thanh Tran, General Conference Chair

Technical Program Overview:  Thomas Büchner, Technical Program Chair

KEYNOTE PRESENTATION: 8:45 a.m. - 9:45 a.m. “SOC Challenges in the Terabit Networks Era” Nick Ilyadis VP and CTO of Enterprise Networking Group, Broadcom 9:45 a.m. - 10:05 a.m. Coffee break   PLENARY PRESENTATIONS: 10:05 a.m. - 11:00 a.m. “Future Trends in PC Computing and their Implications to SoC” Alexander D. Peleg Vice President, Mobility Group Director, Intel Architecture Strategic and Platform Planning Intel Corporation 11:00 a.m. - 11:55 a.m. “Surfing the iSoC Multitechnology Platform: Volumetric Growth beyond Moore's Law” Dr. Kamran Eshraghian President, Eshraghian Laboratories Pty Ltd., and Ferrero Family Chair in Electrical Engineering, University of California, Merced.

11:55 a.m. - 1:30 p.m.  LUNCH (on your own)

Wednesday, September 17 - Afternoon

CONCURRENT SESSIONS
1:30 p.m. – 3:10 p.m.

WA2:  Embedded Systems and Multicore Architectures
Chair: Norbert Schuhmann, Fraunhofer IIS, Germany
Co-chair:

WA2.1     Energy-Optimal Signaling and Ordering of Bits for Area-Constrained Interconnects, Sharath Jayaprakash and Nihar Mahapatra, Michigan State University

WA2.2     A Unified Power Measurement and Management Platform for Pipelined MPSoC Executions, Sungkwan Ku, HanSam Jung and Ki-Seok Chung, Hanyang University, Korea

WA2.3     Partitioned Reuse Cache For Energy-Efficient Soft-Error Protection of Functional Units, Kaushal Gandhi and Nihar Mahapatra, Michigan State University

WA2.4     The Role of Interconnects in the Performance Scalability of Multicore Architectures, Jiangjiang Liu¹ and Nihar Mahapatra², ¹Lamar University and ²Michigan State University

WB2:  System Level Design
Chair: Emrah Acar, IBM
Co-chair: Kaijian Shi, Synopsys

WB2.1    ILP-based Scheme for Timing Variation-aware Scheduling and Resource Binding, Yibo Chen and Yuan Xie, Pennsylvania State University

WB2.2    Exploiting Loop-Level Parallelism on Multi-Core Architectures for the WiMAX Physical Layer, Ying Yi, Wei Han, Adam Major, Ahmet T. Erdogan and Tughrul Arslan, University of Edinburgh, UK

WB2.3    Extensible Software Emulator for Reconfigurable Instruction Cell Based Processors, Mark Muir, Iain Lindsay and Tughrul Arslan, University of Edinburgh, UK

WB2.4    MRPSIM: A TLM Based Simulation Tool for MPSoCs Targeting Dynamically Reconfigurable Processors, Wei Han, Ying Yi, Mark Muir, Ioannis Nousias, Tughrul Arslan and Ahmet Erdogan, University of Edinburgh, UK

3:10 p.m. - 3:30 p.m.  COFFEE BREAK
 

CONCURRENT SESSIONS
3:30 p.m. – 5:10 p.m.

 WA3:  Signal Integrity
Chair: Radu Secareanu, Freescale
Co-chair: Danella Zhao, UL Lafayette

WA3.1    Pseudo-Random Clocking to Enhance Signal Integrity, Selcuk Kose, Emre Salman, Zeljko Ignjatovic and Eby G. Friedman, University of Rochester

WA3.2    Nanoscale On-Chip Decoupling Capacitors, Mikhail Popovich and Eby Friedman, University of Rochester

WA3.3   Built-In Functional Tests for Fast Validation of a 40Gbps Coherent Optical Receiver SoC ASIC, Yuejian Wu, Sandy Thomson, Han Sun, Chandra Bontu and Eric Hall, Nortel

WA3.4     A Multi-Wire Error Correction Scheme for Reliable and Energy Efficient SoC Links using Hamming Product Codes, Bo Fu and Paul Ampadu, University of Rochester

 WB3:  Network on Chip
Chair: Maurizio Palesi, University of Catania, Italy
Co-Chair: Sao-Jie Chen, NTU, Taiwan

WB3.1    Fluidity Concept for NoC: A Congestion Avoidance and Relief Routing Scheme, Ying-Cherng Lan, Michael Chin Chen¹, Alan P. Su², Yu-Hen Hu¹ and Sao-Jie Chen¹, ¹National Taiwan University and ²Springsoft Inc.

WB3.2    Configurable Error Correction for Multi-Wire Errors in Switch-to-Switch SoC Links, Qiaoyan Yu and Paul Ampadu, University of Rochester

WB3.3    Guaranteeing QoS with the Pipelined Multi-Channel Central Caching NoC Communication Architecture, Azeez Sanusi, Nan Wang and Magdy Bayoumi, University of Louisiana at Lafayette

WB3.4    Energy Minimization using a Greedy Randomized Heuristic for the Voltage Assignment Problem in NoC, Pavel Ghosh and Arunabha Sen, Arizona State University

5:10 p.m. - 6:40 p.m.  POSTER SESSION and RECEPTION BUFFET