POSTER SESSION with Reception

Wednesday, Sept. 17
5:10 p.m. – 6:40 p.m.

Chair:
Co-chair:

P.1          Composability in the Time-Triggered System-on-Chip Architecture, Hermann Kopetz, Christian El Salloum, Bernhard Huber, Roman Obermaisser and Christian Paukovits, Vienna University of Technology, Austria

P.2          A Systematic Approach to Synthesis of Verification Test-suites for Modular SoC Designs, Sudhakar Surendran¹, Rubin Parekhji¹ and R Govindarajan², ¹Texas Instruments and ²Indian Institute of Science

P.3          A 300-mV 36-uW Multiphase Dual Digital Clock Output Generator with Self-Calibration, Ming-Hung Chang, Li-Pu Chuang, I-Ming Chang and Wei Hwang, National Chiao-Tung University, Taiwan

P.4          A Resistance Deviation-to-Time Interval Converter for Resistive Sensors, Ji-Man Park and Sung-ik Jun, ETRI, Korea

P.5          Design Methodology for HD Photo Compression Algorithm Targeting a FPGA, Seth Groder and Kenneth Hsu, Rochester Institute of Technology

P.6          Design of Low Flicker Noise Active CMOS Mixer, Shao-Min Hsu, Yuyu Chang and John Choma, University of Southern California

P.7          65nm Sub-Threshold 11t-SRAM for Ultra Low Voltage Applications, Farshad Moradi¹, Dag. T. Wisland¹, Snorre Aunet¹, Hamid Mahmoodi, and Tuan Vu Cao¹, ¹University of Oslo, Norway, and ²San Francisco State University

P.8          Evaluation Of Contrast Limited Adaptive Histogram Equalisation (CLAHE) Enhancement on a FPGA, Phillip David Ferguson¹, Tughrul Arslan², Ahmet Erdogan² and Andrew Parmley³, ¹Institute Of System Level Integration, ²University of Edinburgh, ³Thales Optronoics Ltd.

P.9          Novel Start-Up Circuit with Enhanced Power-Up Characteristic for Bandgap References, Tuan Vu Cao¹, Dag T. Wisland¹, Tor Sverre Lande¹, Farshad Moradi¹ and Young Hee Kim², ¹University of Oslo, Norway, and ²Changwon National University, South Korea

P.10         Unification of Obstacle-Avoiding Rectilinear Steiner Tree Construction, Iris Hui-Ru Jiang, Shung-Wei Lin and Yen-Ting Yu, National Chiao Tung University, Taiwan

P.11         Analysis of retention time under multi-configuration on a DORGA, Daisaku Seto and Minoru Watanabe, Shizuoka University, Japan

P.12         Performance Evaluation of a FFT Using Adaptive Clocking, Hanni Bagnordi and Mabo Ito, University of British Columbia, Canada

P.13         A Comparator-based Switched-capacitor Integrator Using a New Charge Control Circuit, Farhad Alibeygi Parsan and Ahmad Ayatollahi, Iran University of Science and Technology

P.14         Area Efficient Delay-Insensitive and Differential Current Sensing On-Chip Interconnect, Ethiopia Nigussie, Juha Plosila and Jouni Isoaho, Department of Information Technology, University of Turku, Finland

P.15         Temperature Measurement in Content Addressable Memory Cells using Bias-Controlled VCO, Basab Datta and Wayne Burleson, Electrical & Computer Engineering Department, University of Massachusetts-Amherst

P.16         A Coarse-Grained Dynamically Reconfigurable MAC Processor For Power-Sensitive Multi-Standard Devices, Syed Waqar Nabi¹, Cade C. Wells¹ and Wim Vanderbauwhede², ¹Institute for System Level Integration and ²University of Glasgow, UK

P.17         A Multi-mode Sphere Detector Architecture for WLAN Applications, Ramin Shariat-Yazdi and Tad Kwasniewski, Department of Electronics, Carleton University, Canada

P.18         Slack Redistribution in Pipelined Circuits for Enhanced Soft-Error Rate Reduction, Srivathsan Krishnamohan¹ and Nihar Mahapatra², ¹Synopsys Inc. and ²MSU

P.19         Application Development Flow for On-Chip Distributed Architectures, Khalid Latif¹, Moazzam Niazi¹, Tiberiu Seceleanu², Sakir Sezer³ and Hannu Tenhunen¹,¹University of Turku, Finland, ²ABB Corporate Research, and ³Queens University Belfast, Ireland

P.20         A Novel 0.6V CMOS Folded Gilbert-Cell Mixer for UWB Applications, Md. Mahbub Reja, Kambiz Moez and Igor Filanovsky, University of Alberta, Canada