Thursday, September 18 - Morning

CONCURRENT SESSIONS
8:30 a.m. – 10.10 a.m.

TA1:  Low Power Circuit Design
Chair: Sanu Mathew, Intel
Co-chair: Yong-Bin Kim, Northeastern University

TA1.1     A Robust Ultra-Low Power Asynchronous FIFO Memory with Self-Adaptive Power Control, Mu-Tien Chang, Po-Tsang Huang and Wei Hwang, National Chiao Tung University, Taiwan

TA1.2   A Low Power and Low Area Active Clock Deskewing Technique for sub-90nm technologies, Ashok Narasimhan and Ramalingam Sridhar, State University of New York at Buffalo

TA1.3   A Low Power 32 Nanometer CMOS Digitally Controlled Oscillator, Jun Zhao and Yong-Bin Kim, Northeastern University

TA1.4   Pseudo Parallel Architecture for AES with Error Correction, YiXin Su and Jimsoon Mathew, University of Bristol, UK NO SHOW!

TB1:  H.264
Chair: Nagi Naganathan, LSI Corp.
Co-Chair: Ken Hsu, RIT

TB1.1      Invited Paper: Implementing High Definition Video CODEC on TI DM6467 SoC, Jian Wang and Gang Hua, Texas Instruments

TB1.2      A 5.46 mW H.264/AVC Video Stream Parser, Michelle Brown¹ and Kenneth W. Hsu², ¹Intel Corp., and ²Rochester Institute of Technology

TB1.3    A Low-power Design of Quantization for H.264 Video Coding Standard, Michael Michael and Kenneth Hsu, Rochester Institute of Technology

TB1.4    Speed Control for a Hardware Based H.264/AVC Encoder, Chae Eun Rhee, Jin-Su Jung and Hyuk-Jae Lee, Seoul National University, Korea

10:10 a.m. - 10:30 a.m.  COFFEE BREAK

CONCURRENT SESSIONS
10:30 a.m. – 11:45 a.m.

TA2:  Low Power Design Methodologies
Chair: Yong-Bin Kim, Northeastern University
Co-chair: Sanu Mathew, Intel

TA2.1    Power Optimization for FinFET-based Circuits Using Genetic Algorithms, Jin Ouyang and Yuan Xie, Penn State Univ.

TA2.2    In-Situ Self-Aware Adaptive Power Control with Multi-Mode Power Gating Network, Wei-Chih Hsieh and Wei Hwang, National Chiao Tung University, Taiwan

TA2.3    Supply Voltage Selection in Voltage Island based SoC Design, Dipanjan Sengupta and Resve Saleh, Univ. Of British Columbia, Canada

TB2:  Video Processing
Chair: Ken Hsu, RIT
Co-chair: Nagi Naganathan, LSI Corp.

TB2.1    A Multi-Standard Micro-Programmable Deblocking Filter Architecture and its Application to VC-1 Video Decoder, Ricardo Citro¹, Miguel Guerrero², Jae-Beom Lee³ and Maria Pantoja⁴, ¹Intel Corp., ²Nvidia Corp., ³Sarnoff Corp., and ⁴Santa Clara Univ.

TB2.2    Multi-Standard Sub-Pixel Interpolation Architecture for Video Motion Estimation, Liang Lu, John McCanny and Sakir Sezer, Queen's University Belfast, UK

TB2.3   An Efficient Lossless Embedded Compression Engine Using Compacted-FELICS Algorithm, Yu-Yu Lee, Yu-Hsuan Lee and Tsung-Han Tsai, National Central University, Taiwan

11:45 a.m. - 1:30 p.m.
LUNCHEON with guest speaker:

David F. Doody,
Flight Operations Lead, Cassini Mission Support & Services, NASA Jet Propulsion Lab
“Cassini-Huygens at Saturn”

Thursday, September 18 - Afternoon

CONCURRENT SESSIONS
1:30 p.m. – 3:10 p.m.

 TA3:  SRAM Memory Technologies
Chair: Norbert Schuhmann, Fraunhofer IIS, Germany
Co-Chair:

TA3.1     Low-Power Floating Bitline 8-T SRAM Design with Write Assistant Circuits, Hao-I Yang, Ssu-Yun Lai and Wei Hwang, National Chiao-Tung University, Taiwan

TA3.2     A Subthreshold Single Ended I/O SRAM Cell Design for Nanometer CMOS Technologies, Jawar Singh¹, Jimsoon Mathew¹, Dhiraj K. Pradhan¹, and Saraju P. Mohanty^{2 1}University of Bristol,UK, and ²University of North Texas NO SHOW!

TA3.3     Low Power 8-T SRAM Using 32nm Independent Gate FinFET Technology, Young Bok Kim, Yong-Bin Kim and Fabrizio Lombardi, Northeastern University

TA3.4     Failure Analysis for Ultra Low Power Nano-CMOS SRAM Under Process Variations, Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan¹, and Saraju P. Mohanty^{2 1}University of Bristol,UK, and ²University of North Texas NO SHOW!

TB3:  Analog and Mixed-Signal 1

Chair: Hongjiang Song, Intel
Co-chair: Gin-Kou Ma, ITRI

TB3.1   1.5V 0.5mW 2MSPS 10b DAC with Rail-to-Rail Output in 0.13µm CMOS Technology, Fuding Ge, Malay Trivedi, Brent Thomas, William Jiang and Hongjiang Song, Intel Corp.

TB3.2   Statistical Averaging Based Linearity Optimization for High Speed Converter Architectures in Nanoscale Processes, Martin Kosakowski¹, Reimund Wittmann¹ and Werner Schardein², ¹Nokia GmbH, and ²Univ. Dortmund, Germany

TB3.3   A Higher-Order Mismatch-Shaping Method for Multi-Bit Sigma-Delta Modulators, Alexendar Lavzin¹, Mucahit Kozak² and Eby Friedman³, ¹Israel Army, ²Intrinsix Corp., and ³Univ. of Rochester NO SHOW!

TB3.4   A Novel Sub-1 Volt Reference with all CMOS, Sameer Somvanshi¹, Subash Bose², Sakshi Arora³, and Santosh¹, ¹BITS-Pilani, India, ²CEERI-Pilani, India, and ³Stanford University

3:10 p.m. - 3:30 p.m.  COFFEE BREAK

“Hot Topic”
Plenary Presentation
3:30 p.m. – 4:25 p.m.

Dynamic Configuration: Beyond Video Coding Standards
Iain Richardson
Centre for Video Communications, The Robert Gordon University, UK

Panel Discussion
“Ultra-Green Systems-on-Chip -- Hype or reality?”
4:30 p.m. – 6:00 p.m.