TUTORIALS and WORKSHOPS
Embedded Tutorials (included in conference registration)
Friday Afternoon, Sept. 19, 2008
Chair: Kaijian Shi, Synopsys
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Tutorial Workshops (extra fees apply)
Saturday, Sept. 20, 2008
Chair: Kaijian Shi, Synopsys
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Embedded Tutorial A
3:30 p.m. – 5:30 p.m.
Design and Verification of Complex SoC with Configurable, Extensible Processors
Steve Leibson and Grant Martin, Tensilica, Inc., Santa Clara, CA
As SoCs continue to evolve to have more and more programmable elements and processors on them, the opportunity to tune the processors, interconnect and other blocks to match the intended application and gain advantages of performance and energy consumption is one that many designers are still not aware of. Experience on a wide variety of SoC designs has shown that significant increases in SoC performance and reduction in energy consumption are possible through the use of tuned Application-Specific Instruction set Processors (ASIPs), along with the right choices of interconnect structures and associated hardware blocks. This embedded tutorial introduces the audience to the concept of ASIPs and uses practical examples to illustrate how ASIP architectures can be mapped to applications. It also covers a processor-centric design flow for complex SoC and in particular will describe models and methodologies for design, simulation and verification of these devices using the latest Electronic System Level (ESL) methods.
Biographies
Steven Leibson is Tensilica’s Technology Evangelist, formerly serving as the VP of Content and Editor in Chief of Microprocessor Report, Editor in Chief of EDN Magazine, and Founding Editor in Chief of Embedded Developers Journal. His articles have appeared in many industry magazines. His book “Designing SOCs with Configured Cores” is a university textbook. He organized and served as MC for Microprocessor and Embedded Processor Forums. Leibson holds a BSEE from Case Western Reserve University and worked as an engineer and manager for key electronics pioneers including Hewlett-Packard and Cadnetix. Leibson is an IEEE Senior Member.
Grant Martin is a Chief Scientist at Tensilica, Inc. in Santa Clara, California. Before that, Grant worked for Burroughs in Scotland for 6 years; Nortel/BNR in Canada for 10 years; and Cadence Design Systems for 9 years, eventually becoming a Cadence Fellow in their Labs. He received his Bachelor's and Master's degrees in Mathematics (Combinatorics and Optimisation) from the University of Waterloo, Canada, in 1977 and 1978. Grant is a co-author or co-editor of nine books dealing with SoC design, SystemC, UML, modelling, EDA for integrated circuits and ESL/system-level design, including the first book on SoC design published in Russian. He was co-chair of the DAC Technical Programme Committee for Methods for 2005 and 2006. His particular areas of interest include system-level design, IP-based design of system-on-chip, platform-based design, and embedded software. Grant is a Senior Member of the IEEE.
Embedded Tutorial B
3:30 p.m. – 5:30 p.m.
A New Generation of C-Base Synthesis Tool and Domain-Specific Computing
Zhiru Zhang, AutoESL Design Technologies, Inc
The first part of the tutorial presens a platform-based compilation and synthesis system, named xPilot, developed at UCLA. The xPilot provides advanced behavioral synthesis capability for
compiling C, C++ , or SystemC applications to high quality RTL code optimized for a given FPGA or ASIC platforms for logic, interconnects, and memory optimization with flexibile performance and
area trade-off. It includes a number of algorithmic innovations, such as scheduling based on the system of difference constraints, resource binding for distributed memory architectures, simultaneous
register and functional unit binding, etc. The xPilot system has been licensed by AutoESL Design Technologies, Inc. for commercialization. The AutoPilot tool from AutoESL, derived from xPilot,
has been successfully used for a number of FPGA designs. One application of using such C-to-FGPA compilation systems as xPilot or AutoPilot is to enable domain-specific computing using
FPGAs as customized computing engines for accelerating a wide range of applications. The recent developments by AMD to open up its HyperTransport bus and Intel to open up its Front-side Bus
lead to new high-performance computing platforms with high-bandwidth communication between CPUs and FPGAs, which make it possible to develop high-performance, power-efficient domain-specific computing platforms.
In the second part the presenter will share his experience in applying FPGA-based domain-specific computing for a number of computation-intensive applications in many domains, such as multimedia
applications, financial engineering, and computer-aided designs. Very engaging initial results have been achieved, including over 150X improvement in power-performance efficiency.
Biography
Dr. Zhiru Zhang currently serves as Director of Engineering at AutoESL Design Technologies, Inc, a high-tech
startup headquartered in Los Angeles. He had worked for the VLSI CAD Lab at University of California, Los Angeles (UCLA) as a graduate research assistant, and was the key developer of the UCLA xPilot synthesis
system, which addresses several complex system-level and behavior-level synthesis problems.
Dr. Zhang has 18 publications in the area of Electronic Design Automation. He holds M.S. and Ph. D. degrees in
computer science from UCLA, and a B.S. degree in computer science from Peking University. He has received the Outstanding Ph.D. Award from UCLA for the year of 2006-2007.
Saturday Morning Tutorial Workshops
8:30 a.m. - 11:50 a.m.
Flying-Adder On-Chip Frequency Synthesis Architecture
Liming Xiu, Texas Instruments
The construction of on-chip clock circuitry has great impact on both system performance and chip implementation cost. Among the many aspects of the clock circuitry, the most important one is its capability of producing frequencies. Flying-Adder frequency synthesis architecture, one of the latest developments in clock generation circuitry, is such a circuit-level enabler which can help circuit designers and system engineers to create better-performance and/or lower-cost systems. With this technique, many system and software level issues can be investigated from new directions. Compared to the conventional techniques, this method is capable of generating much more frequencies. Furthermore, it provides great controllability to software so that software programmers have the flexibility of creating novel approaches to differentiate their products from the competitors’. In this tutorial, the Flying-Adder architecture will be first introduced. Then, several real systems are used to demonstrate the power of this new frequency synthesis technique.
Biography
Liming Xiu is the inventor of Flying-Adder frequency and phase synthesis architecture which has been used in many commercial products. He has published many peer-reviewed journal papers and holds multiple patents on this architecture. During his career as IC designer, he has worked on various mixed-signal devices in transistor -level. He is also an industry expert on VLSI SoC integration with battle-proven integration experience on several very large chips. In this area, he has one book published: “VLSI Circuit Design Methodology Demystified”. He is Senior Member of Technical Staff at Texas Instruments, general chair of IEEE CAS Society Dallas Chapter, 2006 and 2007.
8:30 a.m. - 11:50 a.m.
Low Power Design under Parameter Variations
Swarup Bhunia, Case Western Reserve University, and Kaushik Roy, Purdue University
Design considerations for low-power operations and robustness with respect to variations typically impose contradictory design requirements. Low-power design techniques such as voltage scaling, dual-Vth and gate sizing can have large negative impact on parametric yield under process variations . In this tutorial, we focus on circuit/architectural design techniques for low power under parameter variations. We consider both logic and memory design and encompass modeling, analysis as well as design methodology to simultaneously achieve low power and variation tolerance. Design techniques to minimize power under parametric yield constraint as well as major process adaptation techniques using voltage scaling, adaptive body biasing or logic restructuring will be presented. Techniques to deal with within-die parameter variations in logic and memory circuits primarily caused by random dopant fluctuations will be discussed. Finally, we will discuss temperature-aware design, dynamic adaptation to temperature and on-going research activities on low-power and variation tolerant multi-core processor design.
Biographies
Swarup Bhunia is currently an assistant professor of Electrical Engineering and Computer Science at Case Western Reserve University. He received his Ph.D. from Purdue University in 2005. He has worked in the semiconductor industry on RTL synthesis, verification, and low power design for about three years. His research interest includes low-power electronics, variation tolerance, adaptive computing and novel test methodologies. He received SRC technical excellence award, 2005, Best paper award in International Conference on Computer Design, 2004, Best paper award in Latin American Test Workshop, 2003 and Best paper nomination in Asia and South Pacific Design Automation Conference, 2006.
Kaushik Roy is currently a Professor and holds the Roscoe H. George Chair of Electrical & Computer Engineering at Purdue University. He received his Ph.D. from the electrical and computer engineering department of the University of Illinois at Urbana-Champaign in 1990. His research interests include VLSI design/CAD for nanoscale technologies, low-power electronics, VLSI testing and reconfigurable computing. Dr. Roy has published more than 400 papers in refereed journals and conferences. Dr. Roy received the NSF Career Award, IBM faculty partnership award, ATT/Lucent Foundation award, SRC Technical Excellence Award and SRC Inventors Award. Dr. Roy is a fellow of IEEE.
8:30 a.m. - 11:50 a.m.
Real-time implementation of H.264 video coding
Iain Richardson, Centre for Video Communications, The Robert Gordon University, UK
The H.264 Advanced Video Coding standard is widely used in video compression applications. Improved compression efficiency (compared with earlier standards such as MPEG-2) comes at a price of increased computational complexity. This poses a challenge for designers of H.264 systems, namely how to achieve good compression performance on platforms with limited computational resources. This workshop will introduce strategies and techniques for dealing with this challenge. Topics covered will include:
- Overview of the H.264/AVC coding model and the main coding "tools".
- Performance analysis: examining the trade-off between compression performance and computational complexity for H.264 coding tools.
- Case study: optimizing mode selection in an H.264 codec.
Who should attend: researchers and industry professionals with an interest in real-time video or multimedia processing.
Biography
Professor Iain Richardson is the Director of the Centre for Video Communications at the Robert Gordon University, Aberdeen, UK. Prof. Richardson specializes in video compression technology, standards and systems. He wrote the world's first book on the well-known H.264 compression standard, has researched and written extensively on MPEG and H.264 video compression and holds several patents. He provides consulting and analysis services to businesses and industry groups. His current research interests include video codec implementation, human perception and video coding, and dynamic configuration of video codecs.
Saturday Afternoon Tutorial Workshops
SA2
1:00 p.m. - 4:20 p.m.
Understanding and Effectively Suppressing the Noise Coupling in Mixed-Signal SOC Applications
Cosmin Iorga, Noisecoupling.com
The understanding of the noise coupling phenomena is essential to semiconductor design engineers who must deal with the challenges of integrating more and more functionality on a single chip. This tutorial provides a practical approach to the analysis of noise coupling mechanisms, the implementation of efficient suppression techniques, and the simulation of noise coupling in various stages of the design flow. The noise generation, propagation, and reception are analyzed at the physical structures of devices, chip substrates, and packages. Various suppression techniques are presented, emphasizing their advantages and limitations. In addition to conventional techniques, circuit level compensation methods and design examples are presented and analyzed. The noise coupling simulation in post-layout, pre-layout, and architectural stages of design is discussed, emphasizing the advantages and limitations specific to each of these stages. A practical approach for modeling the noise coupling early in the architectural stages of the design is also presented.
Biography
Dr. Cosmin Iorga has earned his Ph.D. in electrical engineering form Stanford University. His dissertation focused on noise coupling in integrated circuits. Dr. Iorga has accumulated more than 15 years of experience in circuit design and troubleshooting at system, board, and integrated circuit levels. Dr. Iorga has filed 10+ patents covering innovative solutions in noise coupling reduction and signal integrity. Dr. Iorga is the author of the book "Noise Coupling in Integrated Circuits: A Practical Approach to Analysis, Modeling, and Suppression". Dr . Iorga is president of NoiseCoupling.com, a company that focuses on noise coupling research and education through hands-on workshops.
1:00 p.m. - 4:20 p.m.
Asynchronous Circuit Design using Handshake Solutions
Ad Peeters and Mark de Wit, Handshake Solutions
Asynchronous Circuit Design is a disruptive technology that is going through a silent revolution. Once deemed an eternal promise of the future, today, hundreds of millions of asynchronous circuits are produced every year, and many of us may use it on a daily basis without being aware of it. Asynchronous circuits may now be found in the vast majority of electronic (biometric) passports, in in-vehicle networks like CAN and LIN, in MEMS-based sensors such as for measuring tire pressure, in access-control systems, and in Near Field Communication devices such as Nokia's 6131 NFC phone.
The circuits mentioned above have all been designed using Handshake Solutions' Timeless Design Environment (TiDE). TiDE enables the compilation of energy-efficient asynchronous circuits directly from a behavioral level specification. For the physical implementation standard third-party cell libraries, simulators, placement and route tools, and ATPG tools are used
The tutorial will present an introduction into TiDE and will highlight some of the designs introduced in the market. A hands-on session will introduce a pipelined media-processing design, where the participants design one of the stages using TiDE.
Biographies
Ad Peeters is the CTO of Handshake Solutions. He holds an MSc (1988) and PhD (1996) from Eindhoven University of Technology. In 1991 he started working at Philips Research on the development of asynchronous circuit technology, on which numerous papers and patents have been published. Since 1997, this technology is being commercialized, initially via Philips Semiconductors (now NXP), for instance in the pager, smartcard and automotive markets. In 2004 Handshake Solutions was formed in order to make the design tools and asynchronous technology available to the semiconductor and electronics industry.
Mark de Wit is senior technology engineer in Handshake Solutions with focus on the Timeless Design Environment TiDE. He holds and MSc (2003) from Eindhoven University of Technology. Since joining Handshake Solutions in 2004, Mark has been responsible for the compiler that translates from the behavioral design language Haste into circuit implementations, FPGA views, and simulation languages like behavioral Verilog and system C.