Program04

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CONFERENCE-AT-A-GLANCE

Sunday, September 12 - Tutorial Workshops

Morning Workshops

SA: Analog, Mixed-Signal,
and RF Design
for SOC Applications

SB: SoC Design Methodology
in Deep Submicron Technology

8:00 a.m. -
11:40 a.m.

SA1
Trade-Offs in RF Analog Circuit Design for SOC Applications, S. Kiaei (ASU), S. Farahani, N. Darbanian(ASU), M. H. Smith(Intel), A. Hietala(RF Micro Devices).

SB1
SoC Design Methodology: A Practical Approach, A. Jain (TI, USA) and A. Saha (TI, India).

Afternoon Workshops

1:00 pm -
2:50 pm

SA2
Substrate Coupling Noise and its Reduction through Early Design Planning in Mixed-Signal SoCs, M. Chrzanowska-Jeske and G. Blakiewicz (Portland State University).

SB2
Heterogenenous Modeling of SoCs with System C using Multi-MOC Kernel of System C, H. D. Patel and S. K. Shukla (Virginia Tech).

3:00 p.m. -
4:50 p.m.

SA3
A 243-GHz F_t and 208-GHz F_max , 90-nm SOI CMOS SoC Technology with Low-Power Millimeter-Wave Digital and RF Circuit Capability, N. Zamdmer, J. Kim, R. Trzcinski, J. Plouchart, S. Narasimha (IBM).

SB3
High-Performance CMOS Circuits for Sub-90nm Design, Steven K. Hsu (Intel).

5:00 p.m. -
6:30 p.m.

Opening Reception

Monday, September 13

Registration
7:00 a.m. -
5:00 p.m.

Plenary Session
8:30 a.m. -
11:00 a.m.

Opening Remarks:
   Sung-Mo"Steve" Kang, General Conference Chair
Technical Program Overview:
   Dong Ha, Technical Program Chair
Keynote Presentation:
   Paul E. Jacobs, Executive Vice President and President,
QUALCOMM Wireless & Internet Group
Plenary Presentations:
   Kiyoo Itoh, Fellow, Hitachi, Ltd.,
James D. Meindl, Director, MicrosystemsResearchCenter and Professor, Microsystems, Georgia Institute of Technology

Technical Sessions
11:10 a.m. -
12:00 noon

Track A
MA1:
RECONFIGURABLE
APPLICATIONS

Track B
MB1:
ON-CHIP TESTING OF EMBEDDED SILICON TRANSDUCERS

Track C
MC1: MULTI-THRESHOLD CIRCUITS

Lunch
12:00 noon -
1:10 p.m.

Technical Sessions
1:10 p.m. -
2:50 p.m.

Track A
MA2:
ANALOG TO DIGITAL CONVERSION

Track B
MB2:
SYSTEM LEVEL ARCHITECTURE AND DESIGN

Track C
MC2:
DEEP-SUBMICRON DESIGN

3:10 p.m. -
4:25 p.m.

MA3:
EMBEDDED SYSTEMS

MB3: MULTIMEDIA PROCESSORS

MC3:
DSP CIRCUITS

4:40 p.m. -
6:00 p.m.

POSTER SESSION

Conference Banquet
6:00 p.m. -
8:00 p.m.

Banquet Presentation:
Dr. Michael Riordan, Adjunct Professor, University of California, Santa Cruz

Tuesday, September 14

Registration
7:30 a.m. -
5:00 p.m.

Technical Sessions
8:40 a.m. -
10:20 a.m.

Track A
TA1: EMBEDDED PROCESSORS FOR SOC

Track B
TB1: HIGH PERFORMANCE SYSTEMS AND ARCHITECTURES

10:40 a.m. -
11:55 a.m.

TA2: DESIGN FOR TESTABILITY AND RELIABILITY

TB2: LOW POWER DESIGN

Luncheon
11:55 a.m. -
1:40 p.m.

Guest speaker:
IBM ASIC Design TAT Reduction
Dr. Jürgen Koehl
Distinguished Engineer, IBM Technology Group

Technical Sessions
1:40 p.m. -
3:20 p.m

Track A
TA3: HIGH PEFORMANCE CIRCUITS AND METHODOLOGIES

Track B
TB3: NETWORK PROCESSING ARCHITECTURES AND CIRCUITS

3:40 p.m. -
4:55 p.m.

TA4: RECONFIGURABLE ARCHITECTURES

TB4: VARIOUS ISSUES OF SOC

5:00 p.m. -
7:45 p.m.

ICU Vendor Fair and Reception

Wednesday, September 15

Registration
8:00 a.m. -
3:30 p.m.

Technical Sessions
8:40 a.m. -
10:20 a.m.

Track A
WA1: ANALOG CIRCUITS I

Track B
WB1: INTERCONNECT MODELING

10:40 a.m. -
11:55 a.m.

WA2: WIRELESS COMMUNICATION

WB2: DIGITAL SIGNAL PROCESSING

Lunch
11:55 a.m. - 1:10 p.m.

1:10 p.m. -
2:40 p.m.

Panel Discussion
“Who is in the Driver Seat for SoC Technology: EDA or Design?”

Technical Sessions
2:50 p.m. -
4:50 p.m.

Track A
WA3: ANALOG CIRCUITS II

Track B
WB3: LOW POWER ARCHITECTURE